Design and Analysis of a Novel Low Complexity and Low Power Ping Lock Arbiter by using EGDI based CMOS Technique

Network-on-chip (NoC) provides solution to overcome the complications of on-chip interconnect architecture in multi-core systems. It mainly consists router, links and network interface. An essential component router is an arbiter that significantly impacts performance router. The should provide fast fair arbitration when it placed Critical Path Delay (CPD) main aim this research work design a novel for effective scheduler complex real time applications. At same resource allocation power consumption be very low. Previously, gate level Ping Lock Arbiter (PLA) designed limited Improved Pong (IPPA) with less delay. But chip size are high. To problem, Effective Gate Diffusion Input (EGDI) logic-based CMOS scheme used Compact (CPLA). proposed CPLA compared existing PLA based on static scheme. comparison between conventional carried out analyze area, delay by using Tanner Tool 14.1 250nm 45nm technology. suitable compact smart applications glitch free arbitration. presents 41.2% reduction total area consumption. also 47.12% average Area Power Product (APP) 4-bit PLA. Similarly, 8-bit shows 49.48% APP product shrinkage For low constraint applications, EGDI best ping lock round robin arbiter. Therefore, results demonstrate achieves consumes than